Generally, phase-change materials are capable of being electrically programmed between a first structural state where the material is generally amorphous and a second structural state where the material is generally crystalline. The term “amorphous”, as used herein, refers to a structural condition which is relatively less ordered or more disordered than a single crystal. The term “crystalline”, as used herein, refers to a structural condition which is relatively more ordered than amorphous. The phase-change material exhibits different electrical characteristics depending upon its state. For instance, in its crystalline, more ordered state the material exhibits a lower electrical resistivity than in its amorphous, less ordered state. Each material phase can be conventionally associated with a corresponding logic value. For example, the lower resistance crystalline state may be associated with a logic “1” while the higher resistance amorphous state may be associated with a logic “0”.
Materials that may be used as a phase-change material include alloys of the elements from group VI of the Periodic Table. These group VI elements are referred to as the chalcogen elements and include the elements Te and Se. Alloys that include one or more of the chalcogen elements are referred to as chalcogenide alloys. An example of a chalcogenide alloy which may be used as a phase-change material is the alloy Ge.sub.2Sb.sub.2Te.sub.5 (also referred to as GST225). An example of a chalcogenide alloy which is particularly useful as a threshold switching material is the alloy Si.sub.14Te.sub.39As.sub.37Ge.sub.9X.sub.1 where X may be element In or the element P.
The phase-change materials may change states through application of an electrical signal. The electrical signal may be a voltage across or a current through the phase change material. The electrical signal may be in the form of one or more electrical pulses. As an example, the volume of material may be programmed from its higher resistance reset state (more amorphous) to its lower resistance set state (less amorphous and more crystalline) through application of an electrical pulse (e.g. a current pulse) referred to as a set pulse. While not wishing to be bound by theory, it is believed that the set pulse is sufficient to change at least a portion of the volume of memory material from a less-ordered amorphous state to a more-ordered crystalline state. The volume of material may be programmed back from the low resistance set state to the high resistance reset state by application of an electrical pulse with more amplitude than a set pulse (e.g. a current pulse) referred to as a reset pulse. While not wishing to be bound by theory, it is believed that application of a reset pulse to the volume of material is sufficient to change at least a portion of the volume of memory material from a more-ordered crystalline state to a less-ordered amorphous state. It is conceivable that other forms of energy, including, but not limited to optical energy (such as from a laser), thermal energy, electromagnetic energy or mechanical energy (such as acoustical energy) may be used to change the state of the volume of material.
A phase-change material may be used to form a phase-change memory. Typically, a phase-change memory is arranged as an array of phase-change memory cells having rows and columns with associated word lines and bit lines, respectively. Each memory cell includes a memory element. The memory cell may further include an access device (also referred to in the art as an isolation device or a steering element). The access device may be coupled in series with the memory element. Examples of access devices include (without limitation) diodes, transistors and threshold switching elements. A threshold switching element may also be referred to as threshold switch. A threshold switching element may be formed of a chalcogenide material. A threshold switching element may be formed of an S-type threshold switching material. An example of using a threshold switching element as an access device in provided in U.S. Pat. No. 3,573,757 which is hereby incorporated by reference herein.
In a memory array, each memory cell may be coupled between a respective word line (also referred to as a row line or an X line) and a respective bit line (also referred to as a column line or a Y line).
The memory cells can be selected for a reading operation, for example, by applying suitable voltages to the respective word lines and suitable current or voltage pulses to the respective bit lines. In response to forcing a current into the bit line, the voltage reached at the bit line depends on the resistance of the storage element, i.e., on the logic value stored in the selected memory cell.
For general memory use, either commodity or embedded, the logic value stored in the memory cell may be evaluated by sense amplifiers of the memory. Typically, a sense amplifier includes a comparator receiving the bit line voltage, or a related voltage, and a suitable reference voltage. As an example in response to a current forced into the selected column, if the bit line driven by a read current achieves a voltage that is higher than the reference voltage for having higher resistance than the lower resistance case, the bit may be decreed to correspond to a stored logic value “0”, whereas if the bit line voltage is smaller than the reference voltage for the cell having lower resistance, then the bit may be decreed to correspond to the stored logic value “1”.
Products, such as programmable logic devices, achieve random logic designs by providing standard logic interconnected to user specifications typically through an X-Y grid, although the lines to be interconnected may also be on the same level, with cross-unders used (such as poly or N+). This X-Y grid may be conceptually similar to the X-Y grid of a memory array and consists of X lines (corresponding, for example, to row or word lines) and a plurality of Y lines (corresponding, for example, to column or bit lines). The X lines typically cross (either over or under) the Y lines. The X lines may be oriented in a first direction while the Y lines are all oriented in a second direction different from the first direction. The X lines may be substantially perpendicular to the Y lines. The X lines may be physically spaced apart from the Y lines. The X lines may be insulated from the Y lines, however, it is possible that the X lines may be pre-connected to the Y lines such as through a shorting contact. When interconnecting logic instead of memory elements of a memory array, the X-Y grid may be more random in spacing and irregular in length than the X-Y grid of the memory array.
In a memory array, the impedance between the X lines and the Y lines is preferably very high, like an open circuit, until the select device is enabled, such as by row selection or column selection, or both row and column selection. Such selection may entail lowering or raising the X and/or Y lines. Selecting a particular X line lowers the impedance between a memory element and a corresponding Y line, with the path of impedance not necessarily to the selected X line, but instead being a path, for example, to ground. When the path within the cell is to ground, a select transistor may be used wherein the gate is controlled by the X-line. If the select path within the cell is to the X line, the select device may be, for example, a diode or a threshold switching element. The impedance of certain types of threshold switching element may be reduced when the voltage across the element equals or exceeds a threshold voltage. The element turns on whereby the voltage across the element may then snap back to a holding voltage which is less than the threshold voltage. The threshold switching element may remain on until current through the element drops below a holding current.
In contrast, the X-Y grid of conducting lines used for interconnecting logic (such as in a programmable logic array) may have a relatively linear resistance between the lines instead of the piecewise linear resistance. For a logic device such as a programmable logic array, resistance may be relatively high where no connection (an open circuit) is intended and relatively low where a connection (a short circuit) is intended.
The appropriate connections between the X lines and Y lines at the cross-points determining interconnect among logic gates and electronic functions may be programmed in different ways. One type of programming technology used to selectively determine connections is mask programming. This is done by the semiconductor manufacturer during the chip fabrication process. Examples of mask programmable devices include mask programmable gate arrays, mask programmable logic arrays and mask programmable ROMs. In the case of mask programming, a CLOSED connection may be an actual short circuit (for example, by using a contact or via) between an X line and a Y line at a cross-point, while an OPEN connection may be an actual open circuit (where the lines may be separated by an insulator such as Silicon dioxide or Silicon nitride). This approach may be characterized by good layout efficiency and performance, but higher tooling costs and time delay to first article product, since custom masks and layout are used for each different customer product and these may need to be generated and applied to silicon before the customer specific product is completed.
In contrast to mask programmable devices, field programmable devices are programmed after manufacture. Examples of field programmable devices include programmable ROM (PROM), electrically erasable ROM (EEPROM), field programmable logic arrays (FPLA), the programmable array logic device (PAL.RTM.), the complex programmable logic device (CPLD), and the field-programmable gate array (FPGA).
Field programmable devices make use of programmable connections at the cross-points of the X lines and the Y lines in order to program the device after the time of manufacture, and such programming may be done by the manufacturer to customer specification, or by the OEM upon receipt, or by the end customer in the field, and even updated periodically such as through an internet download (which may update connections or repair bugs found in the field).
For field programmable devices such as field programmable logic arrays (FPLA), the programmable connections may be made so that a relatively high resistance between the lines represents an OPEN connection between the lines while a relatively low resistance represents a CLOSED connection between the lines. Products with relatively lower resistance for CLOSED connections may be faster with improved voltage margin. Margin and speed may also be improved if the capacitance of the programmable connection tied to the interconnected lines is low, as well as the lines and devices interconnected. Programmable connections having a higher resistance for OPEN connections may have lower leakage and better voltage margin, since those connections intended to be OPEN connections may have a voltage difference across the lines (as various levels or logic states are applied to the driver and/or receiver lines). That is, any resistor between the lines bleeds current and increases battery drain, while decreasing the voltage margin.
The power drained off by the cross-points intended to be OPEN is a larger problem in larger logic arrays with more X-Y interconnects, and hence more cross-points. For non-mask programmed field programmable devices, whether tying together logic or other electronic functions, there is a need for a programmable connection that can provide a relatively low resistance in CLOSED connections and a relatively high resistance in OPEN connections. Preferably, the programmable connection shall also add little capacitance to the interconnected conductive lines and change the wafer fabrication process as little as possible.
A programmable connection for a field programmable device, such as a field programmable logic array (FPLA) may be a volatile or non-volatile connection (the difference being whether the device must be re-programmed each time power is restored). For example, when a computer is turned off, the logic pattern desired in the field programmable logic chips may be stored in hard disc. Upon power-on restart, the logic interconnect pattern may be reloaded into the configuration memory elements controlling the interconnect between logic gates and other functions, at the expense of delayed restart. Such a volatile approach, may store the state of the programmable connection at each cross-point node on a static ram (SRAM) driving an n-channel cross point transistor, as shown in FIG. 1.
FIG. 1 shows an example of a programmable connection that uses a conventional SRAM to drive the gate of an n-channel transistor QI at the cross-point. The p-channel pull-up transistors Q2 and Q4, provide a high logic level near the power supply, and the n-channel pull-down transistors Q6 and Q8, provide a pull-down to the lower power supply, in the usual CMOS fashion. Here, the p-channel Q2 and Q4 are also cross coupled into an SRAM so that node N2 or node N4 may be high and the other low. Line PX may select the SRAM through transistor Q12 so that data may be written into the configuration bit from line PY (where the data may be furnished and driven by a processor). Output node N2 drives the gate of a transistor QI, making it conductive when the gate of QI is high, or non-conductive when the gate is driven (by programming the SRAM) to a low or off state. The transistor QI is coupled between the Y conductive line and the X conductive line.
The programmable connection may be characterized by its worst case capacitance and resistance over the voltage and temperature range of the lines interconnected, a lower resistance when “on” providing less delay and better voltage margin. Especially desirable is low on resistance during the transition of the coupled lines from a high to low, or low to high. A higher resistance when “off” (lines not coupled) provides lower leakage and battery drain, as well as improved voltage margin by reducing line and driver voltage drop from leakage.
In the SRAM type programmable connection example version shown in FIG. 1, the source to drain “on” resistance is lower for voltages on the coupled X and Y lines that are less than the power supply to which the gate is driven, since the resistance from source to drain of the n-channel transistor tends to increase when the source and drain voltages approach the gate voltage. Accordingly, in some versions of greater complexity, the n-channel transistor QI may have a special low threshold voltage Vt or the power supply in the configuration control SRAM may be higher than in the logic interconnect area, so the N2 line is high enough that QI is on even when X and Y are high.
Alternately, the n-channel transistor QI may be in parallel with a p-channel with gate driven by node N4. This full mux approach may provide a lower resistance but it may be at the expense of greater capacitance and increased chip area for each matrix switch.
As a further example, to make such an approach non-volatile, the SRAM in FIG. 1 may be replaced by an EPROM, EEPROM, or Flash transistor properly loaded to drive the n-channel interconnect transistor QI, or the SRAM may be mirrored with non-volatile memory such as FeRAM. Programming the non-volatile memory may be accomplished with a special higher voltage or current for the non-volatile element. However, such an approach increases process complexity.
Further, both the SRAM or the non-volatile memory alternative may require considerable area in the base silicon to control the interconnect transistor. In addition, the area of the interconnect transistor coupling the lines uses up area in the base silicon (and grows the chip).
The connections in field programmable devices such as FPLAs may also be made non-volatile by using anti-fuses at the X-Y interconnect as shown in FIG. 2A, which shows anti-fuse 10 coupled between an X line and a Y line. Such products, for example FPLAs and FPGAs, desirably reduce the chip area and layers dedicated to programming the programmable connection, by reducing the semiconductor active devices (by eliminating the SRAM) and interconnect to program the SRAM (e.g. PX and PY) at each switch. This may also free up base silicon by forming the cross-point as a thin-film layer between interconnect layers, thus eliminating the area related to the cross-point transistor that is programmed by the SRAM (or other non-volatile alternatives such as Flash or FeRam or EEprom).
The anti-fuse 10 acts as an OPEN connection before it is programmed. The OPEN connection is characterized by the amount of leakage at maximum voltage between the coupled X-Y lines. The anti-fuse may be implemented using an insulative breakdown material that is broken down to provide a conductive pathway through application of a sufficiently high voltage across the material.
Once programmed to a lower resistance state, an anti-fuse cannot be readily reversed. Accordingly, testing prior to shipping or in the field (at the OEM manufacturer or by the customer) may be difficult, since reversing a programmed anti-fuse may be impractical. Also, subsequent changes in the field, such as by remote connection via modem or internet, may not be possible that could reduce repair and upgrade costs since the anti-fuse, once punctured into a low resistance state, may not be reversible (other than by impractically high current, which may adversely affect reliability). If a high resistance is subsequently needed after programming into a low resistance state at the cross-connect, the chip must be replaced instead of re-programmed.
The anti-fuse 10 may be formed as a metal-metal anti-fuse as shown in FIG. 2B that includes a first metal layer 12A, a second metal layer 12B, an dielectric layer 14 and a breakdown layer 16. The metal layers 12A,B may be formed of an alloy of tungsten, titanium and silicon. The breakdown layer 16 may be formed of an amorphous silicon.
Manufacturers of equipment may find an error in FPLA operation/functionality after programming at the factory and shipment to the customer that could be fixed (if the programming is reversible), perhaps thereby allowing correction such as through remote dial-up or internet access download to re-program the logic. Or, the chip may be removed in the field and re-programmed by plugging into an adaptor to a computer.
However, while such an option is possible with SRAM or its non-volatile re-programmable equivalent (such as Flash, EEPROM, or FeRam), such an option may not be possible with an anti-fuse based approach. Instead, the part must instead be removed and replaced, perhaps at considerable expense to the manufacturer and inconvenience to the customer.
Further, due to the limitations of programming irreversible links, such as anti-fuse based FPGA, in only one direction (to be a short), testing of the arrays intended for use by the customer may be done only indirectly, such as by programming spare (unused) but representative anti-fuses along side the main array of interconnect fuses before a part is shipped. However, actual programming of (untested) links by the customer may be unsuccessful, since the links or cross-points actually used may be defective since they were untested before being shipped or used. Cross-points found unprogrammable may require return of the unit to the factory or even replacement in the final equipment, if personalization is done after assembly.
Each of these discards may be at successively higher cost and require an undesirable manufacturing and field use flow which is incompatible with a more preferred zero-defect manufacturing and use. To better improve “yield” and reduce defects in the field, the size and complexity of irreversible fuse or anti-fuse based approaches may be limited to relatively small arrays of interconnect compared to the more testable SRAM based approaches.
Further, the non-SRAM based approaches may add processing steps beyond those of making the logic to be interconnected, and those extras processing steps may excessively raise cost. Customer preferences for a more testable non-volatile storage with lower cost and lower power suggest that such additional processing steps relative to SRAM are preferably offset by reduced chip size and processing steps.
Accordingly, there is need for a programmable matrix array using non-volatile programmable connections that are reversible both at the factory and in the field.